1. Technical Field
The present disclosure relates to a transmission channel. The disclosure, for example, relates to a transmission channel for ultrasound applications and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
Sonography or ultrasonography is a system of medical diagnostic testing that uses ultrasonic waves or ultrasounds and is based on the principle of the transmission of the ultrasounds and of the emission of echo and is widely used in the internistic, surgical and radiological field.
The ultrasounds being normally used are comprised between 2 and 20 MHz. The frequency is chosen by taking into consideration that higher frequencies have a greater image resolving power, but penetrate less in depth in the subject under examination.
These ultrasounds are normally generated by a piezoceramic crystal inserted in a probe being maintained in direct contact with the skin of the subject with the interposition of a suitable gel (being suitable for eliminating the air between probe and subject's skin, allowing the ultrasounds to penetrate in the anatomic segment under examination). The same probe is able to collect a return signal or echo, which is suitably processed by a computer and displayed on a monitor.
In particular, the ultrasounds that reach a variation point of the acoustic impedance, and thus for example an internal organ, are partially reflected and the reflected percentage conveys information about the impedance difference between the crossed tissues. It is to be noted that, the big impedance difference between a bone and a tissue being considered, with the sonography it is not possible to see behind a bone, which causes a substantially total reflection of the ultrasounds, while air or gas zones give “shade”, causing a partial reflection of the ultrasounds.
The time employed by an ultrasonic wave for carrying out the path of going, reflection and return is provided to the computer, which calculates the depth wherefrom the echo has come, thus identifying the division surface between the crossed tissues (corresponding to the variation point of the acoustic impedance and thus to the depth wherefrom the echo comes).
Substantially, an ultrasonographer, in particular a diagnostic apparatus based on the ultrasound sonography, may comprise three parts:                a probe comprising at least one transducer, in particular of the ultrasonic type, which transmits and receives an ultrasound signal;        an electronic system that drives the transducer for the generation of the ultrasound signal or pulse to be transmitted and receives an echo signal of return at the probe of this pulse, processing in consequence the received echo signal; and        a displaying system of a corresponding sonography image processed starting from the echo signal received by the probe.        
In particular, the word transducer generally indicates an electric or electronic device that converts a type of energy relative to mechanical and physical quantities into electric signals. In a broad sense, a transducer is sometimes defined as any device that converts energy from one form to another, so that this latter can be re-processed, for example, manually, by other machines, or combinations thereof. Many transducers are both sensors and actuators. An ultrasonic transducer usually comprises a piezoelectric crystal that is suitably biased for causing its deformation and the generation of the ultrasound signal or pulse.
A typical transmission channel or TX channel being used in these applications is schematically shown in FIG. 1.
In particular, the transmission channel 1 comprises an input logic 2 that drives, in correspondence with an input bus BUSIN, a level shifter 3, in turn connected to a high voltage buffer block 4. The high voltage buffer block 4 is electrically coupled between pairs of high voltage reference terminals, respectively higher HVP0 and HVP1 and lower HVM0 and HVM1, and has a pair of input terminals, INB1 and INB2, connected to the level shifter 3, as well as a pair of output terminals, OUTB1 and OUTB2, connected to a corresponding pair of input terminals, INC1 and INC2 of a clamping block 5.
Furthermore, the clamping block 5 is connected to a clamp voltage reference terminal PGND and has an output terminal corresponding to a first output terminal HVout of the transmission channel 1, in turn connected, through an antinoise block 6, to a connection terminal Xdcr for the transducer to be driven through the transmission channel 1.
A high voltage switch 7 is electrically coupled between the connection terminal Xdcr and a second output terminal LVout of the transmission channel 1.
More in detail, the high voltage buffer block 4 comprises a first branch comprising a first buffer transistor MB1 and a first buffer diode DB1, electrically coupled, in series to each other, between a first higher voltage reference terminal HVP0 and a buffer central node XBc, as well as a second buffer diode DB2 and a second buffer transistor MB2, being electrically coupled, in series to each other, between the buffer central node XBc and a first lower voltage reference terminal HVM0. The first and the second buffer transistor, MB1 and MB2, have respective control or gate terminals in correspondence with a first XB1 and a second inner circuit node XB2 of the high voltage buffer block 4 and connected to, and driven by, a first buffer input driver DRB1 and a second buffer input driver DRB2, in turn connected to the level shifter 3 in correspondence with the first and the second input terminals, INB1 and INB2, of the high voltage buffer block 4.
The high voltage buffer block 4 also comprises, in parallel to the first branch, a second branch in turn comprising a third buffer transistor MB3 and a third buffer diode DB3, electrically coupled, in series to each other, between a second higher voltage reference terminal HVP1 and the buffer central node XBc, as well as a fourth buffer diode DB4 and a fourth buffer transistor MB4, electrically coupled, in series to each other, between the buffer central node XBc and a second lower voltage reference terminal HVM1. The third and fourth buffer transistor, MB3 and MB4, have respective control or gate terminals in correspondence with a third XB3 and a fourth inner circuit node XB4 of the high voltage buffer block 4 and connected to, and driven by, a third DRB3 and a fourth buffer input driver DRB4, in turn connected to the first XB1 and to the second inner circuit node XB2 and then to the first DRB1 and to the second buffer input driver DRB2, respectively, as well as to a first OUTB1 and to a second output terminal OUTB2.
In particular, in the example of the figure, the first and third buffer transistors, MB1 and MB3, are high voltage P-channel MOS (Metal Oxide Semiconductor) transistors (HV Pmos) while the second and fourth buffer transistors, MB2 and MB4, are high voltage N-channel MOS transistors (HV Nmos). Moreover, the buffer diodes, DB1, DB2, DB3 and DB4, are high voltage diodes (HV diode).
The clamping block 5 has in turn a first input terminal INC1 and a second input terminal INC2, respectively connected to the first OUTB1 and second output terminal OUTB2 of the high voltage buffer block 4.
In particular, the clamping block 5 comprises a first clamp driver DRC1 connected between the first input terminal INC1 and a control or gate terminal of a first clamp transistor MC1, in turn electrically coupled, in series with a first clamp diode DC1, between the clamp voltage reference terminal PGND, in particular a ground, and a clamp central node XCc. The first clamp transistor MC1 and the first clamp diode DC1 are interconnected in correspondence with a first clamp circuit node XC1.
The clamping block 5 also comprises a second clamp driver DRC2 connected between the second input terminal INC2 and a control or gate terminal of a second clamp transistor MC2, in turn electrically coupled, in series with a second clamp diode DC2, between the clamp central node XCc and the clamp voltage reference terminal PGND. The second clamp transistor MC2 and the second clamp diode DC2 are interconnected in correspondence with a second clamp circuit node XC2.
The clamp central node XCc is also connected to the first output terminal HVout of the transmission channel 1, in turn connected to the connection terminal Xdcr through an antinoise block 6 comprising respective first and second antinoise diodes, DN1 and DN2, connected in antiparallel, e.g., by having the anode terminal of the first diode connected to the cathode terminal of the second one and vice versa, between the first output terminal Hvout and the connection terminal Xdcr.
In particular, in the example of the figure, the first clamp transistor MC1 is a high voltage P-channel MOS transistor (HV Pmos) while the second clamp transistor MC2 is a high voltage N-channel MOS transistor (HV Nmos). Moreover, the clamp diodes, DC1 and DC2, are high voltage diodes (HV diode) while the antinoise diodes, DN1 and DN2, are low voltage diodes (LV diode).
When the clamping block 5 is on, the first output terminal HVout is at a voltage value substantially corresponding to the ground voltage value GND.
After a pulse cycle, the anode terminals of the first DB1 and third buffer diode DB3 and the cathode terminals of the second DB2 and fourth buffer diode DB4 stabilize themselves at a voltage depending on different factors such as the supply voltage value, inner capacities, which one and how many transistors are used for the switch, the switching frequency etc.
This means that any successive pulse train finds a different, non-defined initial condition.
By changing the initial status also the output wave form is modified with the consequence that the input control being identical it is possible to obtain different outputs. In other words, the wave form of the output signal is function of the input signals and of the initial condition resulting from the previously occurred switches thus creating a sort of “memory effect”.